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| MCP1726 1A, Low Voltage, Low Quiescent Current LDO Regulator Features * * * * * * * * * * * * * 1A Output Current Capability Input Operating Voltage Range: 2.3V to 6.0V Adjustable Output Voltage Range: 0.8V to 5.0V Standard Fixed Output Voltages: - 0.8V, 1.2V, 1.8V, 2.5V, 3.3V, 5.0V Low Dropout Voltage: 220 mV Typical at 1A Typical Output Voltage Tolerance: 0.4% Stable with 1.0 F Ceramic Output Capacitor Fast response to Load Transients Low Supply Current: 140 A (typ) Low Shutdown Supply Current: 0.1 A (typ) Adjustable Delay on Power Good Output Short Circuit Current Limiting and Overtemperature Protection 3X3 DFN-8 and SOIC-8 Package Options Description The MCP1726 is a 1A Low Dropout (LDO) linear regulator that provides high current and low output voltages in a very small package. The MCP1726 comes in a fixed (or adjustable) output voltage version, with an output voltage range of 0.8V to 5.0V. The 1A output current capability, combined with the low output voltage capability, make the MCP1726 a good choice for new sub-1.8V output voltage LDO applications that have high current demands. The MCP1726 is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. Only 1 F of output capacitance is needed to stabilize the LDO. Using CMOS construction, the quiescent current consumed by the MCP1726 is typically less than 140 A over the entire input voltage range, making it attractive for portable computing applications that demand high output current. When shut down, the quiescent current is reduced to less than 0.1 A. The scaled-down output voltage is internally monitored and a power good (PWRGD) output is provided when the output is within 92% of regulation (typical). An external capacitor can be used on the CDELAY pin to adjust the delay from 1 ms to 300 ms. The overtemperature and short circuit current-limiting provide additional protection for the LDO during system fault conditions. Applications * * * * * * High-Speed Driver Chipset Power Networking Backplane Cards Notebook Computers Network Interface Cards Palmtop Computers 2.5V to 1.XV Regulators Package Types Adjustable (SOIC-8) VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 ADJ 6 CDELAY 5 PWRGD Fixed (SOIC-8) VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 VOUT 6 CDELAY 5 PWRGD Adjustable (3X3 DFN) VIN 1 VIN 2 SHDN 3 GND 4 8 7 6 5 VOUT ADJ CDELAY PWRGD Fixed (3X3 DFN) VIN 1 VIN 2 SHDN 3 GND 4 8 7 6 5 VOUT VOUT CDELAY PWRGD (c) 2005 Microchip Technology Inc. DS21936B-page 1 MCP1726 Typical Application MCP1726 Fixed Output Voltage VIN = 2.3V to 2.8V VOUT = 1.8V @ 1A 1 2 3 4 VIN VIN VOUT 8 VOUT 7 C1 4.7 F SHDN CDELAY 6 GND PWRGD 5 C3 1000 pF R1 100 k C2 1 F On Off PWRGD MCP1726 Adjustable Output Voltage VIN = 2.3V to 2.8V VOUT = 1.2V @ 1A R1 40 k 1 2 3 4 VIN VIN VOUT 8 ADJ 7 C1 4.7 F SHDN CDELAY 6 GND PWRGD 5 C3 1000 pF R3 100 k R2 20 k C2 1 F On Off PWRGD DS21936B-page 2 (c) 2005 Microchip Technology Inc. MCP1726 Functional Block Diagram PMOS VIN VOUT Undervoltage Lock Out (UVLO) ISNS Cf Rf ADJ SHDN Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA - Overtemperature Sensing PWRGD CDELAY (c) 2005 Microchip Technology Inc. DS21936B-page 3 MCP1726 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VIN ....................................................................................6.5V Maximum Voltage on Any Pin .. (GND - 0.3V) to (VDD + 0.3)V Maximum Junction Temperature, TJ ........................... +150C Maximum Power Dissipation ......... Internally-Limited (Note 6) Storage temperature .....................................-65C to +150C DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = (VR + 0.5V) or 2.3V, whichever is greater, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters Input Operating Voltage Input Quiescent Current Input Quiescent Current for SHDN Mode Maximum Output Current Line Regulation Load Regulation Output Short Circuit Current Sym VIN Iq ISHDN IOUT VOUT/ (VOUT x VIN) VOUT/VOUT IOUT_SC Min 2.3 -- -- 1 -- -1.5 -- 140 0.1 -- 0.05 0.5 1.7 Typ Max 6.0 220 3 -- 0.3 1.5 -- Units V A A A %/V % A Note 1 IL = 0 mA, VIN = VR +0.5V, VOUT = 0.8V to 5.0V SHDN = GND VIN = 2.3V to 6.0V (Note 1) (VR + 0.5)V VIN 6V IOUT = 1 mA to 1A, VIN = (VR + 0.6)V (Note 4) VIN = (VR + 0.5)V, RLOAD < 0.1, Peak Current VIN = 2.3V to VIN = 6.0V, IOUT = 1 mA VIN = 6.0V, VADJ = 0V to 6V Conditions Adjust Pin Characteristics Adjust Pin Reference Voltage Adjust Pin Leakage Current Adjust Temperature Coefficient Note 1: 2: 3: 4: 5: 6: VADJ IADJ TCVOUT 0.402 -10 -- 0.410 0.01 40 0.418 +10 -- V nA ppm/C Note 3 7: The minimum VIN must meet two conditions: VIN 2.3V and VIN (VR + 2.5%) + VDROPOUT. VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VR + 0.5V. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150C rating. Sustained junction temperatures above 125C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS21936B-page 4 (c) 2005 Microchip Technology Inc. MCP1726 DC CHARACTERISTICS (Continued) Electrical Specifications: Unless otherwise noted, VIN = (VR + 0.5V) or 2.3V, whichever is greater, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters Fixed-Output Characteristics Voltage Regulation Dropout Characteristics Dropout Voltage Power Good Characteristics Input Voltage Operating Range for Valid PWRGD VPWRGD_VIN 1.0 1.2 PWRGD_THF PWRGD_THR PWRGD Output Voltage Low PWRGD Leakage PWRGD Time Delay VPWRGD_L PWRGD_LK TPG 88 89 89 90 -- -- -- 10 -- Detect Threshold to PWRGD Active Time Delay Shutdown Input Logic-High Input Logic-Low Input SHDN Input Leakage Current Note 1: 2: 3: 4: 5: 6: VSHDN-HIGH VSHDN-Low SHDNILK -0.1 0.001 45 15 +0.1 %VIN %VIN A VIN = 2.3V to 6.0V VIN = 2.3V to 6.0V VIN = 6V, SHDN =VIN, SHDN = GND TVDET-PWRGD -- -- -- 92 92 94 93 0.2 0.1 200 30 300 170 6.0 6.0 96 95 98 96 0.4 -- -- 55 -- -- % % % % V A s ms ms s V TA = +25C TA = -40C to +125C ISINK = 100 A PWRGD Threshold Voltage (Referenced to VOUT) VOUT < 2.5V, Falling Edge VOUT > 2.5V, Falling Edge VOUT < 2.5V, Rising Edge VOUT > 2.5V, Rising Edge IPWRGD SINK = 1.2 mA VPWRGD = VIN = 6.0V CDELAY = OPEN CDELAY = 0.01 F CDELAY = 0.1 F VIN-VOUT -- 220 500 mV IOUT = 1A, VIN(MIN) = 2.3V (Note 5) VOUT VR 2.5% VR 0.5% VR + 2.5% V Note 2 Sym Min Typ Max Units Conditions 7: The minimum VIN must meet two conditions: VIN 2.3V and VIN (VR + 2.5%) + VDROPOUT. VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VR + 0.5V. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150C rating. Sustained junction temperatures above 125C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. (c) 2005 Microchip Technology Inc. DS21936B-page 5 MCP1726 DC CHARACTERISTICS (Continued) Electrical Specifications: Unless otherwise noted, VIN = (VR + 0.5V) or 2.3V, whichever is greater, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters AC Performance Output Delay From SHDN Output Noise TOR eN -- 100 2.0 -- s SHDN = GND to VIN VOUT = GND to 95% VR Sym Min Typ Max Units Conditions V/Hz IOUT = 200 mA, f = 1 kHz, COUT = 1 F (X7R Ceramic), VOUT = 2.5V dB f = 100 Hz, COUT = 10 F, IOUT = 100 mA, VINAC = 30 mV pk-pk, CIN = 0 F IOUT = 100 A, VOUT = 1.8V, VIN = 2.8V IOUT = 100 A, VOUT = 1.8V, VIN = 2.8V Power Supply Ripple Rejection Ratio PSRR -- 54 -- Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: 2: 3: 4: 5: 6: TSD TSD -- -- 150 10 -- -- C C 7: The minimum VIN must meet two conditions: VIN 2.3V and VIN (VR + 2.5%) + VDROPOUT. VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VR + 0.5V. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150C rating. Sustained junction temperatures above 125C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V. Parameters Temperature Ranges Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8LD 3 x 3 DFN JA -- 41 -- C/W 4-Layer JC51-7 Standard Board with vias 4-Layer JC51-7 Standard Board TJ TJ TA -40 -- -65 -- -- -- +125 +150 +150 C C C Steady State Transient Sym Min Typ Max Units Conditions Thermal Resistance, 8LD SOIC JA -- 150 -- C/W DS21936B-page 6 (c) 2005 Microchip Technology Inc. MCP1726 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. NOTE: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25C. 180 Quiescent Current (A) 0.05 Line Regulation (%/V) VR = 1.2V (Adj.) IOUT = 0 mA +125C +25C 170 160 150 140 130 120 110 100 0.04 IOUT = 1A VR = 1.2V (Adj.) VIN = 2.3V to 6.0V 0.03 0.02 0.01 0 -0.01 -0.02 5 20 35 50 65 80 95 110 110 IOUT = 1 mA IOUT = 100 mA IOUT = 500 mA -40C 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 Input Voltage (V) Temperature (C) FIGURE 2-1: Quiescent Current vs. Input Voltage (1.2V Adjustable). 300 FIGURE 2-4: Line Regulation vs. Temperature (1.2V Adjustable). 0.70 Ground Current (A) 280 260 240 220 200 180 160 140 120 VR = 1.2V (Adj.) VR = 5.0V Load Regulation (%) 0.60 0.50 0.40 0.30 0.20 0.10 -40 -25 -10 20 35 50 65 80 95 VR = 0.8V VIN = VR + 0.6V (or 2.3V) IOUT = 1 mA to 1A VR = 1.8V VR = 3.3V VIN = 3.3V VIN = 2.5V 0 200 400 600 800 1000 Load Current (mA) Temperature (C) FIGURE 2-2: Ground Current vs. Load Current (1.2V Adjustable). 160 Quiescent Current (A) 150 140 130 120 110 100 5 20 35 50 65 80 95 110 125 -40 -25 -10 VIN = 2.5V FIGURE 2-5: Temperature. 411.00 Adjust Pin Voltage (mV) Load Regulation vs. VR = 1.2V (Adj.) IOUT = 0 mA VIN = 5.0V VIN = 3.3V IOUT = 1 mA 410.50 410.00 409.50 409.00 408.50 5 20 35 50 65 80 95 110 125 -40 -25 -10 VIN = 6.0V VIN = 2.3V Temperature (C) Temperature (C) FIGURE 2-3: Quiescent Current vs. Junction Temperature (1.2V Adjustable). FIGURE 2-6: Temperature. Adjust Pin Voltage vs. (c) 2005 Microchip Technology Inc. DS21936B-page 7 125 5 125 -40 -25 -10 MCP1726 NOTE: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25C. 250 225 200 175 150 125 100 75 50 25 0 0 180 Quiescent Current (A) Adjustable Version Dropout Voltage (mV) 170 160 150 140 130 120 110 100 2.3 VOUT = 0.8V IOUT = 0 mA +125C VOUT = 5.0V VOUT = 2.5V +90C +25C -40C 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 200 400 600 800 1000 Output Current (mA) Input Voltage (V) FIGURE 2-7: Dropout Voltage vs. Output Current (Adjustable Version). 270 Dropout Voltage (mV) 260 250 240 230 220 210 200 190 5 20 35 50 65 80 95 110 125 -40 -25 -10 VOUT =2.5V VOUT = 5.0V VOUT = 3.3V FIGURE 2-10: Quiescent Current vs. Input Voltage (0.8V Fixed). 800 Quiescent Current (A) Adjustable Version IOUT = 1A 700 600 500 400 300 200 100 0 +25C +125C VOUT =3.3V IOUT = 0 mA -40C 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 5.9 Input Voltage (V) Temperature (C) FIGURE 2-8: Dropout Voltage vs. Temperature (Adjustable Version). Power Good Time Delay (ms) FIGURE 2-11: Quiescent Current vs. Input Voltage (3.3V Fixed). 340 320 300 280 260 240 220 200 180 160 140 120 0 32 VIN =3.0V VIN = 2.3V for 0.8V device 28 26 24 22 CDELAY = 10 nF VIN =5.5V Ground Current (A) 30 VIN =2.3V VOUT =3.3V VOUT =0.8V 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 200 400 600 800 1000 Temperature (C) Load Current (mA) FIGURE 2-9: Power Good (PWRGD) Time Delay vs. Temperature. FIGURE 2-12: Current. Ground Current vs. Load DS21936B-page 8 (c) 2005 Microchip Technology Inc. 5.9 MCP1726 NOTE: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25C. 170 Quiescent Current (A) Line Regulation (%/V) 160 150 140 130 120 110 100 IOUT = 0 mA VIN = 2.3V for 0.8V Device VOUT =3.3V 0.025 0.02 0.015 0.01 0.005 0 -0.005 -0.01 VOUT = 3.3V IOUT =1A IOUT =500 mA IOUT =100 mA VOUT =0.8V IOUT =1 mA -40 -25 -10 5 20 35 50 65 80 95 110 125 5 110 Temperature (C) Temperature (C) FIGURE 2-13: Temperature. 100 90 80 70 60 50 40 30 20 10 0 -40 Quiescent Current vs. FIGURE 2-16: Line Regulation vs. Temperature (3.3V Fixed). 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 Load Regulation (%) VOUT =1.8V VOUT =0.8V VOUT =1.2V ISHDN (nA) VIN =6.0V VIN =3.3V VIN =2.3V IOUT = 1 mA to 1000 mA VIN = 2.3V 5 20 35 50 65 80 95 110 125 5 20 35 50 65 80 95 110 110 Temperature (C) Temperature (C) FIGURE 2-14: ISHDN vs. Temperature. FIGURE 2-17: Load Regulation vs. Temperature (VOUT < 2.5V Fixed). -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 -0.55 -0.60 -0.65 -0.70 0.015 Line Regulation (%/V) 0.005 0 -0.005 -0.01 -0.015 -0.02 -0.025 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature (C) IOUT =100 mA VOUT = 0.8V IOUT =500 mA IOUT =10 mA Load Regulation (%) 0.01 IOUT =1.0A VOUT =5.0V VOUT =3.3V VOUT =2.5V IOUT = 1 mA to 1000 mA VIN = VOUT + 0.6V Temperature (C) FIGURE 2-15: Line Regulation vs. Temperature (0.8V Fixed) FIGURE 2-18: Load Regulation vs. Temperature (VOUT 2.5V Fixed). (c) 2005 Microchip Technology Inc. DS21936B-page 9 125 -40 -25 -10 5 20 35 50 65 80 95 125 -25 -10 -40 -25 -10 125 -40 -25 -10 20 35 50 65 80 95 MCP1726 NOTE: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25C. 250 225 200 175 150 125 100 75 50 25 0 0 200 10 VOUT =2.5V (Adj) IOUT = 200 mA Dropout Voltage (mV) Noise (V Hz) VOUT =5.0V VOUT =2.5V 1 VOUT =0.8V (Fixed) IOUT = 100 mA 0.1 COUT =1 F CIN = 10 F 400 600 800 1000 0.01 0.01 0.1 1 10 100 1000 Load Current (mA) Frequency (kHz) FIGURE 2-19: Current. 270 260 250 240 230 220 210 200 190 180 -40 -25 Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Density vs. Frequency. 80 70 60 PSRR (dB) IOUT = 1A Dropout Voltage (mV) VOUT = 1.2V VIN = 2.5V VOUT =5.0V VOUT =3.3V 50 40 30 20 COUT =10 F CIN = 0 F IOUT = 100 mA VOUT =2.5V 10 20 35 50 65 80 95 110 125 0 0.01 -10 5 0.1 1 10 100 1000 Temperature (C) Frequency (kHz) FIGURE 2-20: Temperature. Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.). 90 80 70 PSRR (dB) 60 50 40 30 20 10 COUT =22 F CIN = 0 F IOUT = 100 mA 1.7 Short Circuit Current (A) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 5.9 Input Voltage (V) VOUT =1.2V (Fixed) VOUT = 1.2V VIN = 2.5V 0 0.01 0.1 1 10 100 1000 Frequency (kHz) FIGURE 2-21: Input Voltage. Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.). DS21936B-page 10 (c) 2005 Microchip Technology Inc. MCP1726 NOTE: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25C. 80 70 60 PSRR (dB) 50 40 30 20 10 COUT =10 F CIN = 0 F IOUT = 100 mA VOUT = 2.5V VIN = 3.3V VOUT PWRGD SHDN 1 10 100 1000 0 0.01 0.1 Frequency (kHz) FIGURE 2-25: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed). 80 70 60 PSRR (dB) 50 40 30 20 10 COUT =22 F CIN = 0 F IOUT = 100 mA FIGURE 2-28: Shutdown. 2.5V (Adj.) Startup from VOUT = 2.5V VIN = 3.3V VOUT PWRGD VIN 1 10 100 1000 0 0.01 0.1 Frequency (kHz) FIGURE 2-26: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed). FIGURE 2-29: Power Good (PWRGD) Timing with CBYPASS of 1000 pF. VOUT VOUT PWRGD PWRGD VIN VIN FIGURE 2-27: 2.5V (Adj.) Startup from VIN. FIGURE 2-30: Power Good (PWRGD) Timing with CBYPASS of 0.01 F. (c) 2005 Microchip Technology Inc. DS21936B-page 11 MCP1726 NOTE: Unless otherwise indicated, VIN = VOUT + 0.5V, IOUT = 1 mA and TA = +25C. 3.3V VIN 2.3V VOUT CIN = 1 F COUT = 10 F IOUT = 100 mA VOUT CIN = 47 F COUT = 10 F IOUT VIN FIGURE 2-31: (1.2V Fixed). Dynamic Line Response FIGURE 2-33: Dynamic Load Response (2.5V Fixed, 10 mA to 1000 mA). 4.5V 3.5V VIN VOUT CIN = 47 F COUT = 10 F VOUT CIN = 1 F COUT = 10 F IOUT = 100 mA IOUT VIN FIGURE 2-32: (2.5V Fixed). Dynamic Line Response FIGURE 2-34: Dynamic Load Response (2.5V Fixed, 100 mA to 1000 mA). DS21936B-page 12 (c) 2005 Microchip Technology Inc. MCP1726 3.0 PIN DESCRIPTION PIN FUNCTION TABLE Pin No. Adjustable Output 1 2 3 4 5 6 7 -- The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No. Fixed Output 1 2 3 4 5 6 -- Name VIN VIN SHDN GND PWRGD CDELAY ADJ VOUT VOUT EP Description Input Voltage Supply Input Voltage Supply Shutdown Control Input (active-low) Ground Power Good Output Power Good Delay Set-Point Input Output Voltage Sense Input (adjustable version) Regulated Output Voltage Regulated Output Voltage Exposed Pad of the DFN Package 7 8 Exposed Pad 8 Exposed Pad 3.1 Input Voltage Supply (VIN) 3.5 Connect the unregulated or regulated input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 1 F to 10 F should be sufficient for most applications. Power Good Delay Set-Point Input (CDELAY) 3.2 Shutdown Control Input (SHDN) The CDELAY input sets the power-up delay time for the PWRGD output. By connecting an external capacitor from the CDELAY pin to ground, the delay times for the PWRGD output can be adjusted from 200 s (no capacitance) to 300 ms (0.1 F capacitor). This allows for the optimal setting of the system reset time. The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the PWRGD output also goes low and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1 A. 3.6 Output Voltage Sense Input (ADJ) The output voltage adjust pin (ADJ) for the adjustable output voltage version of the MCP1726 allows the user to set the output voltage of the LDO by using two external resistors. The adjust pin voltage is 0.41V (typical). 3.3 Ground (GND) 3.7 Regulated Output Voltage (VOUT) Connect the GND pin of the LDO to a quiet circuit ground. This will help the LDO power supply rejection ratio and noise performance. The ground pin of the LDO only conducts the quiescent current of the LDO (typically 140 A), so a heavy trace is not required. The VOUT pin(s) is the regulated output voltage of the LDO. A minimum output capacitance of 1.0 F is required for LDO stability. The MCP1726 is stable with ceramic, tantalum and aluminum-electrolytic capacitors. See Section 4.3 "Output Capacitor" for output capacitor selection guidance. 3.4 Power Good Output (PWRGD) 3.8 Exposed Pad (EP) The PWRGD output is an open-drain output used to indicate when the LDO output voltage is within 92% (typically) of its nominal regulation value. The PWRGD output has a typical hysteresis value of 2% for the adjustable voltage version and for voltage outputs less than 2.5V. For fixed output voltage versions greater than 2.5V, the hysteresis is 0.7%. The PWRGD output is delayed on power-up by 200 s (typical, no capacitance on CDELAY pin). This delay time is controlled by the CDELAY pin. (c) 2005 Microchip Technology Inc. The 3X3 DFN package has an exposed pad on the bottom of the package. This pad should be soldered to the Printed Circuit Board (PCB) to aid in the removal of heat from the package during operation. The exposed pad is at the ground potential of the LDO. DS21936B-page 13 MCP1726 4.0 DEVICE OVERVIEW 4.2 The MCP1726 is a high output current, Low Dropout (LDO) voltage regulator with an adjustable delay power-good output and shutdown control input. The low dropout voltage of 220 mV at 1A of current makes it ideal for battery-powered applications. Unlike other high output current LDOs, the MCP1726 only draws 220 A of quiescent current at full load. Output Current and Current Limiting The MCP1726 LDO is tested and ensured to supply a minimum of 1A of output current. The MCP1726 has no minimum output load, so the output load current can go to 0 mA and the LDO will continue to regulate the output voltage to within tolerance. The MCP1726 also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload condition (usually represents a shorted load condition), the output current is limited to 1.7A (typical). If the overload condition is a soft overload, the MCP1726 will supply higher load currents of up to 3A. The MCP1726 should not be operated in this condition continuously as it may result in failure of the device. However, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 1A or less. Output overload conditions may also result in an overtemperature shutdown of the device. If the junction temperature rises above 150C, the LDO will shut down the output voltage. See Section 4.9 "Overtemperature Protection" for more information on overtemperature shutdown. 4.1 LDO Output Voltage The MCP1726 LDO is available with either a fixed output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.5V for both versions. 4.1.1 ADJUST INPUT The adjustable version of the MCP1726 uses the ADJ pin (pin 7) to get the output voltage feedback for output voltage regulation. This allows the user to set the output voltage of the device with two external resistors. The nominal voltage for ADJ is 0.41V. Figure 4-1 shows the adjustable version of the MCP1726. Resistors R1 and R2 form the resistor divider network necessary to set the output voltage. With this configuration, the equation for setting VOUT is: EQUATION 4-1: R1 + R 2 V OUT = V ADJ ------------------ R2 VOUT = LDO Output Voltage VADJ = ADJ Pin Voltage (typically 0.41V) 4.3 Output Capacitor The MCP1726 requires a minimum output capacitance of 1 F for output voltage stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 2 ohms. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 F X7R 0805 capacitor has an ESR of 50 milli-ohms. Larger LDO output capacitors can be used with the MCP1726 to improve dynamic performance and power supply ripple rejection performance. A maximum of 22 F is recommended. Aluminum-electrolytic capacitors are not recommended for low-temperature applications of < -25C. MCP1726-ADJ VIN C1 4.7 F 1 VIN 2 VIN 4 GND VOUT 8 ADJ 7 VOUT R1 3 SHDN CDELAY 6 On Off PWRGD 5 C2 1 F C3 1000 pF R2 FIGURE 4-1: Typical adjustable output voltage application circuit. The allowable resistance value range for resistor R2 is from 10 k to 200 k. Solving the equation for R1 yields the following equation: EQUATION 4-2: V OUT - V ADJ R1 = R2 -------------------------------- V ADJ VOUT = LDO Output Voltage VADJ = ADJ Pin Voltage (typically 0.41V) DS21936B-page 14 (c) 2005 Microchip Technology Inc. MCP1726 4.4 Input Capacitor Low input source impedance is necessary for the LDO output to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 F to 4.7 F is recommended for most applications. For applications that have output step load requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. For good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO. The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking 1.2 mA (VPWRGD < 0.4V maximum). VPWRGD_TH VOUT TPG VOH TVDET_PWRGD PWRGD VOL FIGURE 4-2: Power Good Timing. 4.5 Power Good Output (PWRGD) VIN TOR 70 ms The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see the Electrical Characteristics table for Min/Max specs) of its nominal regulation value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as TPG in the Electrical Characteristics table). The power good time delay is adjustable via the CDELAY pin of the LDO (see Section 4.6 "CDELAY Input"). By placing a capacitor from the CDELAY pin to ground, the power good time delay can be adjusted from 200 s (no capacitance) to 300 ms (0.1 F capacitor). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition low. The power good circuitry has a 170 s delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure 4-2 for power good timing characteristics. When the LDO is put into Shutdown mode using the SHDN input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. The timing diagram for the power good output when using the shutdown input is shown in Figure 4-3. 30 ms SHDN TPG VOUT PWRGD FIGURE 4-3: Shutdown. Power Good Timing from 4.6 CDELAY Input The CDELAY input is used to provide the power-up delay timing for the power good output, as discussed in the previous section. By adding a capacitor from the CDELAY pin to ground, the PWRGD power-up time delay can be adjusted from 200 s (no capacitance on CDELAY) to 300 ms (0.1 F of capacitance on CDELAY). See the Electrical Characteristics table for CDELAY timing tolerances. (c) 2005 Microchip Technology Inc. DS21936B-page 15 MCP1726 Once the power good threshold (rising) has been reached, the CDELAY pin charges the external capacitor to 1.5V (typical, this level can vary between 1.4V and 1.75V across the input voltage range of the part). The PWRGD output will transition high when the CDELAY pin voltage has charged to 0.42V. If the output falls below the power good threshold limit during the charging time between 0.0V and 0.42V on the CDELAY pin, the CDELAY pin voltage will be pulled to ground, thus resetting the timer. The CDELAY pin will be held low until the output voltage of the LDO has once again risen above the power good rising threshold. A timing diagram showing CDELAY, PWRGD and VOUT is shown in Figure 4-4. (turn-on) to the LDO output being in regulation is typically 100 s. See Figure 4-5 for a timing diagram of the SHDN input. TOR 400 ns (typ) 30 s 70 s SHDN VOUT VOUT VPWRGD_TH FIGURE 4-5: Diagram. 1.5V (typ) Shutdown Input Timing TPG 0V CDELAY CDELAY Threshold (0.42V) 4.8 Dropout Voltage and Undervoltage Lockout PWRGD Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a VR + 0.5V differential applied. The MCP1726 LDO has a very low dropout voltage specification of 220 mV (typical) at 1A of output current. See the Electrical Characteristics table for maximum dropout voltage specifications. The MCP1726 LDO operates across an input voltage range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.18V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 2.04V (typical). Since the MCP1726 LDO undervoltage lockout activates at 2.04V as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.9V. For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops between the input voltage source and the LDO. For applications with input voltages near 2.3V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. FIGURE 4-4: Diagram. CDELAY and PWRGD Timing 4.7 Shutdown Input (SHDN) The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage of the input voltage. The typical value of this shutdown threshold is 30% of VIN, with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. The SHDN input will ignore low-going pulses (pulses meant to shut down the LDO) that are up to 400 ns in pulse width. If the shutdown input is pulled low for more than 400 ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal. On the rising edge of the SHDN input, the shutdown circuitry has a 30 s delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the 30 s delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30 s delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high DS21936B-page 16 (c) 2005 Microchip Technology Inc. MCP1726 4.9 Overtemperature Protection The MCP1726 LDO has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150C. If the LDO junction temperature does reach 150C, the LDO output will be turned off until the junction temperature cools to approximately 140C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section 5.0 "Application Circuits/Issues" for more information on LDO power dissipation and junction temperature. (c) 2005 Microchip Technology Inc. DS21936B-page 17 MCP1726 5.0 5.1 APPLICATION CIRCUITS/ISSUES Typical Application In addition to the LDO pass element power dissipation, there is power dissipation within the MCP1726 as a result of quiescent or ground current. The power dissipation as a result of the ground current can be calculated using the following equation: The MCP1726 is used for applications that require high LDO output current and a power good output. MCP1726-2.5 VIN = 3.3V 1 VIN C1 10 F On Off 2 VIN VOUT 8 VOUT 7 R1 10k C2 10 F VOUT = 2.5V @ 1A EQUATION 5-2: P I ( GND ) = VIN ( MAX ) x I VIN PI(GND) = Power dissipation due to the quiescent current of the LDO VIN(MAX) = Maximum input voltage IVIN = Current flowing in the VIN pin with no LDO output current (LDO quiescent current) The total power dissipated within the MCP1726 is the sum of the power dissipated in the LDO pass device and the P(IGND) term. Because of the CMOS construction, the typical IGND for the MCP1726 is 140 A. Operating at a maximum of 3.63V results in a power dissipation of 0.51 milli-Watts. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the MCP1726 is +125C. To estimate the internal junction temperature of the MCP1726, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RJA) of the device. The thermal resistance from junction to ambient for the 3X3DFN package is estimated at 41 C/W. 3 SHDN CDELAY 6 4 GND PWRGD 5 C3 1000 pF PWRGD FIGURE 5-1: 5.1.1 Typical Application Circuit. APPLICATION CONDITIONS Package Type = 3X3DFN8 Input Voltage Range = 3.3V 10% VIN maximum = 3.63V VIN minimum = 2.97V VOUT typical = 2.5V IOUT = 1.0A maximum 5.2 5.2.1 Power Calculations POWER DISSIPATION EQUATION 5-3: T J ( MAX ) = P TOTAL x R JA + T AMAX TJ(MAX) = Maximum continuous junction temperature PTOTAL = Total device power dissipation RJA = Thermal resistance from junction to ambient TAMAX = Maximum ambient temperature The internal power dissipation within the MCP1726 is a function of input voltage, output voltage, output current and quiescent current. The following equation can be used to calculate the internal power dissipation for the LDO. EQUATION 5-1: P LDO = ( VIN ( MAX ) ) - V OUT ( MIN ) ) x I OUT ( MAX ) ) PLDO = LDO Pass device internal power dissipation VIN(MAX)= Maximum input voltage VOUT(MIN) = LDO minimum output voltage DS21936B-page 18 (c) 2005 Microchip Technology Inc. MCP1726 The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. The following equation can be used to determine the package maximum internal power dissipation. 5.3 Typical Application Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation is calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: P D ( MAX ) ( T J ( MAX ) - T A ( MAX ) ) = --------------------------------------------------R JA 5.3.1 Package POWER DISSIPATION EXAMPLE Package Type = 3X3DFN PD(MAX) = Maximum device power dissipation TJ(MAX) = maximum continuous junction temperature TA(MAX) = maximum ambient temperature RJA = Thermal resistance from junction to ambient Input Voltage VIN = 3.3V 10% LDO Output Voltage and Current VOUT = 2.5V IOUT = 1.0A Maximum Ambient Temperature TA(MAX) = 70C Internal Power Dissipation PLDO(MAX) = (VIN(MAX) - VOUT(MIN)) x IOUT(MAX) PLDO = (3.3V x 1.1) - (0.975 x 2.5V)) x 1.0A PLDO = 1.192 Watts EQUATION 5-5: T J ( RISE ) = P D ( MAX ) x R JA TJ(RISE) = Rise in device junction temperature over the ambient temperature PD(MAX) = Maximum device power dissipation RJA = Thermal resistance from junction to ambient Device Junction Temperature Rise The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. The thermal resistance from junction to ambient (RJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. The EIA/JEDEC specification is JESD51-7 "High Effective Thermal Conductivity Test Board for Leaded Surface-Mount Packages". The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, "A Method to Determine How Much Power a SOT23 Can Dissipate in an Application" (DS00792), for more information regarding this subject. TJ(RISE) = PTOTAL x RJA TJRISE = 1.192 W x 41.0 C/W TJRISE = 48.8C EQUATION 5-6: T J = T J ( RISE ) + T A TJ = Junction temperature TJ(RISE) = Rise in device junction temperature over the ambient temperature TA = Ambient temperature (c) 2005 Microchip Technology Inc. DS21936B-page 19 MCP1726 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: TJ = TJRISE + TA(MAX) TJ = 48.8C + 70.0C TJ = 118.8C As you can see from the result, this application will be operating very near the maximum operating junction temperature of 125C. The PCB layout for this application is very important as it has a significant impact on the junction-to-ambient thermal resistance (RJA) of the 3X3 DFN package, which is very important in this application. Maximum Package Power Dissipation at 70C Ambient Temperature 3X3DFN (41 C/W RJA) PD(MAX) = (125C - 70C) / 41 C/W PD(MAX) = 1.34W SOIC8 (150C/Watt RJA) PD(MAX) = (125C - 70C)/ 150 C/W PD(MAX) = 0.366W From this table you can see the difference in maximum allowable power dissipation between the 3X3 DFN package and the 8-pin SOIC package. This difference is due to the exposed metal tab on the bottom of the DFN package. The exposed tab of the DFN package provides a very good thermal path from the die of the LDO to the PCB. The PCB then acts like a heatsink, providing more area to distribute the heat generated by the LDO. DS21936B-page 20 (c) 2005 Microchip Technology Inc. MCP1726 6.0 6.1 PACKAGING INFORMATION Package Marking Information 8-Lead DFN (3X3) XXXX XYWW NNN Voltage Option 0.8V 1.2V 1.8V 2.5V 3.3V 5.0V Adj 8-Lead SOIC (150 mil) Code CAAA CAAB CAAC CAAD CAAE CAAF AADJ Example: CAAA E543 256 Example: XXXXXXXX XXXXYYWW NNN 17260802E SN e3 ^^0543 256 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2005 Microchip Technology Inc. DS21936B-page 21 MCP1726 8-Lead Plastic Dual Flat No Lead Package (MF) 3x3x0.9 mm Body (DFN) - Saw Singulated D p b n L EXPOSED METAL PAD E E2 PIN 1 ID INDEX AREA (NOTE 2) 2 1 TOP VIEW D2 BOTTOM VIEW ALTERNATE EXPOSED PAD CONFIGURATIONS A1 A A3 EXPOSED TIE BAR (NOTE 1) Units Dimension Limits n p A A1 A3 E E2 D D2 b L INCHES NOM 8 .031 .000 .026 BSC .035 .001 .008 REF. .118 BSC .118 BSC .012 .016 .039 .002 MILLIMETERS* NOM 8 0.65 BSC 0.80 0.90 0.00 0.02 0.20 REF. 3.00 BSC 1.40 3.00 BSC 2.15 0.30 0.23 0.20 0.40 MIN MAX MIN MAX Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Exposed Pad Width Overall Width Exposed Pad Length Contact Width Contact Length 1.00 0.05 (Note 3) .055 .085 .009 .008 .069 .096 .015 .020 1.75 2.45 0.37 0.50 (Note 3) *Controlling Parameter Notes: 1. Package may have one or more exposed tie bars at ends. 2. Pin 1 visual index feature may vary, but must be located within the hatched area. 3. Exposed pad dimensions vary with paddle size. 4. JEDEC equivalent: MO-229 Drawing No. C04-062 Revised 03/11/05 DS21936B-page 22 (c) 2005 Microchip Technology Inc. MCP1726 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil Body (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 (c) 2005 Microchip Technology Inc. DS21936B-page 23 MCP1726 NOTES: DS21936B-page 24 (c) 2005 Microchip Technology Inc. MCP1726 APPENDIX A: REVISION HISTORY Revision B (March 2005) * Replaced 3x3 DFN package diagram. * Emphasized (bolded) a few specifications of Section 1.0 "Electrical Characteristics" in the DC Characteristics table. Revision A (February 2005) Original Release of this Document. (c) 2005 Microchip Technology Inc. DS21936A-page 25 MCP1726 NOTES: DS21936A-page 26 (c) 2005 Microchip Technology Inc. MCP1726 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Tape & Reel -XXX Voltage Output X X XX Package Examples: a) b) c) Device Tape & Reel Standard Output Voltage * MCP1726:1A, Low Quiescent Current LDO Regulator T = Tape and Reel Blank = Tube 080 = 0.80V 120 = 1.20V 180 = 1.80V 250 = 2.50V 330 = 3.30V 500 = 5.00V ADJ = Adjustable Voltage Version * Custom output voltages available upon request. Contact your local Microchip sales office for more information. Tolerance Temperature Range 2 = 2.0% E = -40C to +125C d) e) f) g) MCP1726-0802E/MF: 0.8V, 1A LDO, 8LD DFN Pkg. MCP1726-1202E/SN: 1.20V, 1A LDO, 8LD SOIC Pkg. MCP1726T-1802E/MF:Tape and Reel, 1.80V, 1A LDO, 8LD DFN Pkg. MCP1726-2502E/SN: 2.50V, 1A LDO, 8LD SOIC Pkg. MCP1726T-3302E/MF:Tape and Reel, 3.30V, 1A LDO, 8LD DFN Pkg. MCP1726-5002E/SN: 5.00V, 1A LDO, 8LD SOIC Pkg. MCP1726-ADJE/MF: Adjustable, , 1A LDO, 8LD DFN Pkg. Tolerance Temp. Range Package * SN = Plastic SOIC, (150 mil Body) 8-Lead MF = Plastic Dual Flat No Lead, 3x3 mm Body (DFN), 8-Lead *Both packages are Lead Free. (c) 2005 Microchip Technology Inc. DS21936B-page 27 MCP1726 NOTES: DS21936B-page 28 (c) 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2005 Microchip Technology Inc. DS21936B-page 29 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 ASIA/PACIFIC India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/01/05 DS21936B-page 30 (c) 2005 Microchip Technology Inc. |
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